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As the increasing in chip density, on-chip communication will be a key factor in determining the performance and power consumption of the multi-core processor. Some typical communication mechanisms of the multi-core processor at present are introduced in detail in this paper, such as cache-shared bus structure, shared-bus structure and NoC-based structure,(More)
Design and Implementation of network on chip interconnection architecture for eight compute-intensive processors are mainly presented in this paper. Firstly, through analysis and comparison of three common NoC topologies, 2×4 2D Turos is chosen as the final topology, and the single routing node architecture is designed, including packet format,(More)
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