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Interconnect delay is becoming a major roadblock to FPGA performance with technology scaling and growing chip sizes. Globally Asynchronous Locally Synchronous (GALS) design is considered a potential solution to this issue. An important design decision in building a GALS FPGA architecture is to determine the appropriate GALS island size. A large GALS island(More)
This paper proposes GAPLA: a globally asynchronous locally synchronous programmable logic array architecture. The whole FPGA area is divided into locally synchronous blocks wrapped with asynchronous I/O interfaces. Data communications between synchronous blocks are controlled by 2-phase handshaking signals. The size and shape of each locally synchronous(More)
In the paper, a new multi-sensor platform for adaptive driving assistance system is introduced. The platform is composed of multi-radar, multi-camera, combined positioning and navigation equipment, and some information can also be obtained from vehicle CAN bus. With the platform and the technique such as multicast network, the information such as road(More)
Hepatic stellate cell (HSC) activation is a key cellular event in the development of liver fibrosis. Peroxisome proliferator-activated receptor-gamma (PPARgamma) has been shown to function as a key transcription regulator linked to suppressing HSC activation. Compelling evidence indicates that leptin plays a unique role in the development of liver fibrosis.(More)
This paper proposes GAPLA: a Globally Asynchronous Locally Synchronous Programmable Logic Array architecture. The whole FPGA area is divided into locally synchronous blocks wrapped with asynchronous I/O interfaces. Data communications between synchronous blocks are controlled by 2-phase handshaking signals under bundled-data delay assumption. The size and(More)
Routing delays dominate other delays in current FPGA designs. We have proposed a novel Globally Asynchronous Locally Synchronous (GALS) FPGA architecture called the GAPLA to deal with this problem. In the GAPLA architecture, The FPGA area is divided into locally synchronous blocks and the communications between them are through asynchronous I/O interfaces.(More)
The performance of FPGAs is suffering from interconnect delays, especially the delays of the long wires which can be more than 10ns in large FPGAs. We have proposed the GAPLA: a globally asynchronous locally synchronous (GALS) FPGA architecture to deal with this problem. In GAPLA architecture, the whole FPGA area is divided into locally synchronous blocks(More)