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When the response to a test vector is captured by state elements in scan based tests, the switching activity of the circuit may be large resulting in abnormal power dissipation and supply current demand. High supply current may cause excessive supply voltage droops leading to larger gate delays which may cause good chips to fail tests. This paper presents a(More)
This paper presents a new and comprehensive low-power test scheme compatible with a test compression environment. The key contribution of this paper is a flexible test-application framework that achieves significant reductions in switching activity during all phases of scan test: loading, capture, and unloading. In particular, we introduce a new on-chip(More)
Supply current and power dissipation during scan based test may be much higher than during normal circuit operation due to larger switching activity caused by the tests. Higher peak current demands may cause supply voltage droops causing good chips to fail at-speed tests. Higher average switching activity causes higher power dissipation and chip temperature(More)
This paper addresses delay test for SOC devices with high frequency clock domains. A logic design for on-chip high-speed clock generation, implemented to avoid expensive test equipment, is described in detail. Techniques for on-chip clock generation, meant to reduce test vector count and to increase test quality, are discussed. ATPG results for the proposed(More)
In this paper, we propose a novel programmable logic BIST controller that can facilitate at-speed test for the design with multiple clock domains and multiple clock frequencies. Moreover, a static analysis method is also proposed to optimize the BIST test pattern allocation for testing the timing faults in different intra/inter clock domains when the(More)
In this paper, a test generation based partial scan selection procedure is proposed. The procedure is able to achieve the same level of fault coverage as in a full scan design by scanning only a subset of the flip-flops. New measures are used to guide the flip-flop selection during the procedure. The proposed procedure is applied to the ISCAS-89 and the(More)