• Publications
  • Influence
A Unified 4/8/16/32-Point Integer IDCT Architecture for Multiple Video Coding Standards
This work proposes a fast computational algorithm of large size integer IDCT, which can support the following video standards: MPEG-2/4, H.264, AVS, VC-1 and HEVC.
Strategies for Reducing Decoding Cycles in Stochastic LDPC Decoders
This brief presents three strategies, including initialization based on Look Up Table (LUT), postprocessing based on bit flipping and hard decision based on the posterior information, to reduce the
An 847–955 Mb/s 342–397 mW Dual-Path Fully-Overlapped QC-LDPC Decoder for WiMAX System in 0.13 $\mu$m CMOS
This paper presents a partially-parallel dual-path fully-overlapped QC-LDPC decoder for the WiMAX system. By adopting five techniques including symmetrical six-stage pipelining, block column and row
A 1.5-D Multi-Channel EEG Compression Algorithm Based on NLSPIHT
A new 2-D arranging method that exploits correlations between different sub-bands is developed to concentrate the energy, which causes more efficient compression using No List Set Partitioning in Hierarchical Trees (NLSPIHT) algorithm, which results in lower computational complexity and power dissipation.
A Pipelined 2D Transform Architecture Supporting Mixed Block Sizes for the VVC Standard
A unified block-based transform architecture for the VVC standard that enables 2D Discrete Sine Transform-VII (DST-VII) and Discrete Cosine Transform -VIII (DCT-VIII) of all sizes and can reduce area by up to 73.1% compared with other state-of-the-art works.
An Energy-Efficient Design for ECG Recording and R-Peak Detection Based on Wavelet Transform
This brief presents an ASIC design for both ECG recording and R-peak detection that leads to a large reduction in the whole system energy by supporting data compression and using a dual-ping-pong-memory architecture.
Fast QTMT Partition Decision Algorithm in VVC Intra Coding based on Variance and Gradient
This is the first attempt to apply traditional method to accelerating the rectangular partition problem in VVC intra prediction and can save averagely 53.17% encoding time with only 1.62% BDBR increase and 0.09dB BDPSNR loss compared to anchor VTM4.0.
VPQC: A Domain-Specific Vector Processor for Post-Quantum Cryptography Based on RISC-V Architecture
Experimental results show that VPQC can speed up several typical key encapsulation mechanisms (NewHope, Kyber and LAC) by an order of magnitude compared with previous state-of-the-art hardware implementations.
A high-throughput VLSI architecture for deblocking filter in HEVC
A four-stage pipeline hardware architecture on a quarter-LCU basis of deblocking filter in HEVC is proposed, which can support 4K×2K (4096×2048) at 30 fps applications with merely 28 MHz working frequency.
An Area-Efficient and Low-Power Multirate Decoder for Quasi-Cyclic Low-Density Parity-Check Codes
This paper presents an improved all-purpose multirate iterative decoder architecture for QC-LDPC codes, which can largely reduce their area and power.