Xiaotao Chen

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Power consumption is an important factor in chip design. The fundamental design decisions drawn during early design space exploration at electronic system level (ESL) have a large impact on the power consumption. This requires to estimate power already at ESL, which is usually not possible using standard ESL component libraries due to missing power models.(More)
Complex many-core architectures are seen as the solution to tackle the computational workloads of the next years. To find the best trade-off between power and performance, different processor architectures have to be considered and evaluated in a thorough and power-aware design space exploration. This is highly facilitated by electronic system level (ESL)(More)
Diagnosing performance violations is one of the biggest challenges in transaction level modeling of systems. In this paper, we propose a methodology to localize root causes of latency or throughput violations. We present a concurrent pattern mining approach to infer frequent patterns from transaction traces to localize root causes. We apply three categories(More)
Power estimation has become a strongly desired feature in Electronic System Level (ESL) simulations. Most existing power estimation approaches for this abstraction level require component models with observable internals. However, most ESL models of modern processors are delivered as black box components. This work presents a tool-based ESL power estimation(More)
Early design space exploration at Electronic System Level (ESL) can be done either using untimed functional models, timed functional models or performance models, which use random or zero data instead of the actual data. In order to be applicable to the two latter types, ESL power estimation approaches often rely only on sub-block activity information. This(More)
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