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A reduced interface and high performance embedded system architecture (MSBUS) is proposed in this paper. The control bus is low-cost and low-power, whereas the data bus is high-bandwidth and high-speed especially. In addition, a Universal Verification Methodology (UVM)-based performance evaluation methodology is proposed to estimate the hardware structures.(More)
Simulation speed and a lack of test approaches are the main difficulties in the mixed-signal verification of a complex System-on-a-Chip (SoC). In this paper, an equivalent high-level Radio Frequency (RF) model is created by the SystemVerilog language and integrated into a mixed-signal SoC. Such a model can be executed on a digital simulator, which is(More)
This paper proposes a high efficiency data bus (DBUS) for Advanced Encryption Standard (AES) encrypted system-on-chips (SoCs). Using DBUS, the data sequence can be pre-selected for AES encryption/decryption, so that the state buffering and rescheduling overhead can be reduced. FPGA results show that the DBUS based design lowers the dynamic energy to 66.93%,(More)
Pedestrian dead reckoning (PDR) is a promising complementary technique to balance the requirements on both accuracy and costs in outdoor and indoor positioning systems. In this paper, we propose a unified framework to comprehensively tackle the three sub problems involved in PDR, including step detection and counting, heading estimation and step length(More)
Epidermal growth factor inhibitors (EGFRIs), the first targeted cancer therapy, are currently an essential treatment for many advance-stage epithelial cancers. These agents have the superior ability to target cancers cells and better safety profile compared to conventional chemotherapies. However, all responding patients eventually developed acquired(More)
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