Xiaoheng Chen

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Designers are increasingly relying on field-programmable gate array (FPGA)-based emulation to evaluate the performance of low-density parity-check (LDPC) codes empirically down to bit-error rates of and below. This requires decoding architectures that can take advantage of the unique characteristics of a modern FPGA to maximize the decoding throughput. This(More)
Non-binary low-density parity-check (NB-LDPC) codes are robust to various channel impairments. The excessive computational complexity and memory usage of the existing decoder designs are considerably expensive for practical applications. Based on a newly proposed simplified min-sum algorithm, which only has 0.05–0.1 dB performance loss against the(More)
This paper presents an FPGA-based implementation of a tri-mode decoder for decoding the cyclic (4095,3367) Euclidean geometry LDPC code which has minimum distance 65 and no trapping set of size less than 65. The implementation integrates three compatible decoding algorithms in a single decoder. The three decoding algorithms are the one-step majority-logic(More)
Artesunate (ART) has high prophylactic efficacy against Schistosoma japonicum infections and has been used to treat and prevent schistosomiasis in China since 1995. However, the molecular mechanism of ART's effects on S. japonicum remains unclear. Herein, we applied isobaric tagging reagents for relative and absolute quantification analyses coupled with(More)
FPGAs are widely used for evaluating the error-floor performance of LDPC (low-density parity check) codes. We propose a scalable vector decoder for FPGA-based implementation of quasi-cyclic (QC) LDPC codes that takes advantage of the high bandwidth of the embedded memory blocks (called Block RAMs in a Xilinx FPGA) by packing multiple messages into the same(More)
Non-binary LDPC codes are effective in combating burst errors. This paper presents an efficient architecture for implementing non-binary LDPC decoders. The Galois field power representation is used to organize the a priori, a posteriori, and extrinsic messages involved in decoding. The power representation in conjunction with the barrel shifter and(More)
There is an increasing need for configurable quasicyclic low-density parity-check (QC-LDPC) decoders that can support a family of structurally compatible codes instead of a single code. The key component in a configurable QC-LDPC decoder is a programmable circular-shift network that supports cyclic shifts of any size up to a predefined maximum submatrix(More)
Non-binary low-density parity-check codes are robust to various channel impairments. However, based on the existing decoding algorithms, the decoder implementations are expensive because of their excessive computational complexity and memory usage. Based on the combinatorial optimization, we present an approximation method for the check node processing. The(More)
We explore the use of Data-Level Parallelism (DLP) as a way of improving the energy efficiency and power consumption involved in running applications on an FPGA. We show that static power consumption is a significant fraction of the overall power consumption in an FPGA and that it does not change significantly even as the area required by an architecture(More)