Xiaofeng Yi

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In this paper, a 4.8GHz fully integrated low power, low phase noise NMOS LC voltage-controlled oscillator (VCO) is presented. The tail resistor and low-pass filter of the bias current mirror are used to obtain good phase noise with little additional area. It is implemented in a 0.18 mum IP6M CMOS process. The chip consumes 4 mA from a 1.8 V supply and(More)
In this paper, a 4.8 GHz fully integrated low power, low phase noise phase-locked loop (PLL) frequency synthesizer ready for WLAN application is presented. It is implemented in a 0.18 mum IP6M CMOS process. The chip consumes only 16 mA (including local buffers to the receiver and transmitter) from a 1.8 V supply and occupies an area of 1.85times1.1(More)
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