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—High performance computing is becoming increasingly important in the field of financial computing, as the complexity of financial models continues to increase. Many of these financial models do not have a practical close form solution in which case numerical methods are the only alternative. Monte-Carlo simulation is one of most commonly used numerical(More)
This paper presents a LO generation system used in multimode global navigation satellite system (GNSS) receivers in 55 nm CMOS. This system contains two PLL frequency synthesizers (FS) and supports simultaneous receiving of any two bands among GPS/GLONASS/Galileo/Compass systems with a flexible frequency plan. An optimized automatic frequency calibration(More)
A model for the single poly EEPROM cells is proposed in this paper, which gives an expression of the floating gate potential. Combining this model and the gate current data of the tunneling transistor, we find a method to implement the transient simulation of the memory cell, including program and erase operations. In the end, an extension of the proposed(More)
A noise and intermodulation distortion (IMD) analysis of CMOS downconverters, such as the widely used CMOS Gilbert cell, is presented. A qualitative physical model has been developed to explain the mechanisms responsible for noise and IMD in mixers. The contribution of all internal noise source and IMD to the output current is calculated through simple(More)
—This paper presents a direct-conversion, multi-standard TV receiver implemented in a 0.13 µm CMOS technology occupying less than 4 mm². The receiver is compliant with several direct broadcasting satellite (DBS) standards, including DVB-S, DVB-S2, and ABS-S. A novel automatic frequency tuning (AFT) technique is adopted based on a searching algorithm to(More)
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