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In this paper, we review the logical effort model presented in [1]. Based on the HSPICE simulation results using 0.18µm, CMOS technology as applied to logic blocks used in arithmetic circuits; we analyze the efficiency of the model and also present modifications that include modeling of wire delay. We propose a new model for logical effort that will better(More)
We present an equation-based transistor size optimizer that minimizes delay of custom circuits. Our method uses static timing analysis to find the critical paths and numerical methods to optimize transistor sizes continuously without using simulation. Consequently, it is faster than simulation-based optimizers, and more general than standard cell(More)
This paper presents an efficient multi-mode weight selection method for joint prediction based coding. This scheme makes use of multi-mode joint prediction of motion estimation/disparity estimation (ME/DE) instead of existing three-mode prediction for reconstructing a target image. Moreover, a fast ME/DE approach is introduced in order to improve the coding(More)
Introduction of sub-90nm technology has made a profound impact on circuit designs. Thus, it requires understanding of existing design styles for desired energy-efficiency. We compare adder designs in the energy-delay space, implemented with Limited Switch Dynamic Logic (LSDL) and Compound Domino Logic (CD) in a 65nm SOI technology. Evaluation results show(More)
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