Xiao-Ping Huang

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The tag sorting circuit in Weighted Fair Queuing (WFQ) is crucial to the Quality of Service (QoS). In this paper, we present a kind of optimized hardware architecture for fast tag sorting, which consists of one-hot encoding and leading zero counting. The architecture is parallel and pipelining. It is implemented using FPGA technology. In comparison with the(More)
For the stream-like applications with high-bandwidth and low latency, optimizing the memory latency can effectively improve the QoS. In this paper, we propose a dedicated adaptive loop pre-fetch mechanism to reduce the memory latency and also improve the pre-fetch accuracy. In the mechanism, when a loop sequences is detected, the stream pre-fetch engine can(More)
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