Learn More
This paper presents a novel heterogeneous multi-core Digital Signal Processor, named <i>YHFT-QDSP</i>, hosting one RISC CPU core and four VLIW DSP cores. The CPU core is responsible for task scheduling and management, while the DSP cores take charge of speeding up data processing. The YHFT-QDSP provides three kinds of interconnection communication. One is(More)
In this paper, we present a lookup table based model for delay and power estimation of low-swing interconnects: LSIEM. It can be used during high-level design planning, synthesis, and simulation of interconnect-centric VDSM designs. LSIEM is an accurate and efficient high-level estimation model. It has been tested on a wide range of parameters and shown to(More)
  • 1