Xianglong Huang

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As improvements in processor speed continue to outpace improvements in cache and memory speed, poor locality increasingly degrades performance. Because copying garbage collectors move objects, they have an opportunity to improve locality. However, no static copying order is guaranteed to match program traversal orders. This paper introduces <i>online(More)
Current user-mode machine simulators typically do not support simulation of dynamic compilation, threads, or garbage collection, all of which Java Virtual Machines (JVMs) require. In this paper, we describe, evaluate, and validate Dynamic SimpleScalar (DSS). DSS is a tool that simulates Java programs running on a JVM, using just-in-time compilation,(More)
Almost all modern operating systems, from Windows to Unix, support multithreaded programming. To make sure our students can lead the trend of computer science in the foreseeable future, we need to introduce them to this important technology. However, we have found through experience in teaching multithreaded programming that the paradigm shift from(More)
Poor code locality degrades application performance by increasing memory stalls due to instruction cache and TLB misses. This problem is particularly an issue for large server applications written in languages such as Java and C# that provide just-in-time (JIT) compilation, dynamic class loading, and dynamic recompilation. However, managed runtimes also(More)
Abstract: The Impulse memory controller provides an interface for remapping irregular or sparse memory accesses into dense accesses in the cache memory. This capability significantly increases processor cache and system bus utilization, and previous work shows performance improvements from a factor of 1.2 to 5 with current technology models for hand-coded(More)
| Multithreading is a powerful programming paradigm that has become very popular in recent years. The authors have developed a set of course materials and software tools for eeectively teaching multithreaded programming (MTP). One important component of the au-thors' system is a very simple user-level kernel for instructors to teach MTP without getting into(More)
Embedded systems require maximum performance from a processor within significant constraints in power consumption and chip cost. Using software pipelining, processors can often exploit considerable instruction-level parallelism (ILP), and thus significantly improve performance, at the cost of substantially increasing register requirements. These increasing(More)
Poor instruction cache locality can degrade performance on modern architectures. For example, our simulation results show that eliminating all instruction cache misses improves performance by as much as 16% for a modestly sized instruction cache. In this paper, we show how to take advantage of dynamic code generation in a Java Virtual Machine (VM) to(More)