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—Power grid verification has become an indispensable step to guarantee a functional and robust chip design. Vectorless power grid verification methods, by solving linear programming (LP) problems under current constraints, enable worst-case voltage drop predictions at an early stage of design when the specific waveforms of current drains are unknown. In(More)
— Reliable design of power distribution network for stacked integrated circuits introduces new challenges i.e., substrate coupling among through silicon vias (TSVs) and tiers grid in addition to reliability issues such as electromigration and thermo-mechanical stress, compared to conventional System on Chip (SoC). In this paper a comprehensive modeling of(More)
—In this paper, an efficient framework is proposed to analyze the worst case of voltage variation of power network considering multidomain clock gating. First, a frequency-domain-based simulation method is proposed to obtain the time-domain voltage response. With the vector fitting technique, the frequency-domain responses are approximated by a partial(More)
This work proposes reliability aware through silicon via (TSV) planning for the 3D stacked silicon integrated circuits (ICs). The 3D power distribution network is modeled and extracted in frequency domain which includes the impact of skin effect. The worst case power noise of the 3D power delivery networks (PDN) with local TSV failures resulting from(More)
Different interconnection structures have been proposed to solve the performance limitation caused by scaling of on-chip global wires. In this paper, we give an overview of current on-chip global interconnection structures and provide a simple model to analyze their architecture-level performance metrics. For a new category of global interconnections using(More)
A frequency-time-domain co-simulation flow using discrete Fourier transform (DFT) is introduced in this paper to analyze large power distribution networks (PDN's). The flow not only allows designers to gain an insight to the frequency-domain characteristics of the PDN but also to obtain accurate time-domain voltage responses according to different load(More)
—As process technology scales, numerous interconnect schemes have been proposed to mitigate the performance degradation caused by the scaling of on-chip global wires. In this paper, we review current on-chip global interconnect structures and develop simple models to analyze their architecture-level performance. We propose a general framework to design and(More)