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We present a single event transient (SET) propagation model that can be used to quantify the propagation likelihood of a given noise waveform trough CMOS logic gates. This analysis is key to predict if an SET induced within a combinational block is capable of causing an SEU. The model predicts the output noise characteristics given the input noise waveform(More)
We present a STA tool based on a single-pass true path computation that efficiently determines the critical path list Given that it does not rely on a two-step process it can be programmed to find efficiently the N true paths from a circuit We also report and analyze the dependence of complex gates delay with the sensitization vector and its variation (that(More)
We present a complete EDA tool that quantifies the susceptibility of each node within a combinational circuit to SET propagation. The tool includes a fully analytical SET propagation model developed previously and considers both electrical and logic masking. After an initial path pruning phase based on logical analysis to determine true paths, the tool(More)
We report and analyze the dependence of complex gates delay with the sensitization vector and its variation-that gets up to 40% in 65-nm CMOS technologies-and include its effect in the path delay estimation-that can be in the order of 16%. The gate delay is computed from a simple polynomial analytical description that requires a one-time library parameter(More)
We analyze the benefits of replacing selected MOSFET transistors by nanoelectromechanical relays within conventional CMOS six transistor SRAM cells. Specifically, we evaluate a potential implementation that uses a cantilever designed with a 65 nm standard CMOS technology. The impact on various reliability metrics like static noise margin and write noise(More)
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