Xabier Iturbe

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The foundations for building the first Reliable Reconfigurable Real-Time Operating System (R3TOS) are presented. The main objective of R3TOS is to create an infrastructure for coordinately executing specialized hardware tasks upon a reconfigurable FPGA device, achieving the necessary flexibility for both gaining system performance (true hardware(More)
—This paper presents the details of a novel technique which allows for the implementation and execution of completely relocatable hardware tasks onto dynamically reconfigurable FP-GAs. Our novel technique harnesses the internal configuration access port (ICAP) for inter-task communication and synchronization , leading to very little logic overheads. The(More)
An Autonomous Fault-Tolerant System (AFTS) refers to a system that is able to configure its own resources in the presence of permanent defects and spontaneous random faults occurring in its silicon substrate in order to maintain its func-tionality. This work analyzes how AFTS could be built, specifically focusing on hardware platform dependant issues, and(More)
—This paper describes a novel scheduling algorithm for the execution of hardware tasks with real-time constraints onto partially and dynamically reconfigurable FPGAs. The Area-Time response Balancing scheduling algorithm (ATB) is inspired by the well-known Earliest Deadline First (EDF) algorithm, which is extended with a technique for reducing the(More)
This paper presents a new Single Event Upset (SEU), Multiple Bit Upset (MBU) and Single Hardware Error (SHE) mitigation strategy to be used in Virtex-4 FPGAs. This strategy aims to increase not only the effectiveness of traditional Triple Module Redundancy (TMR), but also the overall system availability. Frame readback with ECC detection and frame scrubbing(More)
—In this paper we present " Snake", a novel technique for allocating and executing hardware tasks onto partially reconfigurable Xilinx FPGAs. Snake permits to alleviate the bottleneck introduced by the Internal Configuration Access Port (ICAP) in Xilinx FPGAs, by reusing both intermediate partial results and previously allocated pieces of circuitry.(More)
—This paper deals with online scheduling and allocation of real-time hardware tasks onto partially reconfig-urable Xilinx FPGAS. We present a novel fault-aware online allocator which ensures the correctness of the computation by circumventing the permanent damage in the chip. The allocator is merged with an EDF-based scheduler to make up a highly-Reliable(More)