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An Energy-Efficient Micropower Neural Recording Amplifier
TLDR
We present an ultralow-power neural recording amplifier that achieves input-referred noise near the theoretical limit of any amplifier using a differential pair as an input stage. Expand
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A Low-Power 32-Channel Digitally Programmable Neural Recording Integrated Circuit
TLDR
We report the design of an ultra-low-power 32-channel neural-recording integrated circuit (chip) in a 0.18 μ m CMOS technology. Expand
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Low-Power Circuits for Brain–Machine Interfaces
TLDR
This paper presents work on ultra-low-power circuits for brain–machine interfaces with applications for paralysis prosthetics, stroke, Parkinson's disease, epilepsy, prosthetics for the blind. Expand
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Efficient Universal Computing Architectures for Decoding Neural Activity
The ability to decode neural activity into meaningful control signals for prosthetic devices is critical to the development of clinically useful brain– machine interfaces (BMIs). Such systems requireExpand
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Graphical analysis and design of multistage operational amplifiers with active feedback Miller compensation
TLDR
In this paper, we present a graphical design approach for two-stage and three-stage op-amps with active feedback Miller compensation. Expand
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A biomimetic adaptive algorithm and low-power architecture for implantable neural decoders
TLDR
Algorithmically and energetically efficient computational architectures that operate in real time are essential for clinically useful neural prosthetic devices. Expand
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Low-Power Circuits for Brain-Machine Interfaces
TLDR
This paper presents work on ultra-low-power circuits for brain-machine interfaces with applications for paralysis prosthetics, prosthetics for the blind, and experimental neuroscience systems. Expand
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Design of a low-power high open-loop gain operational amplifier for capacitively-coupled instrumentation amplifiers
TLDR
We present the design of a low-power high open-loop gain opamp for use in chopper-stabilized capacitively coupled instrumentation amplifiers (CCIAs). Expand
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A Sub-Microwatt Class-AB Super Buffer: Frequency Compensation for Settling-Time Improvement
TLDR
This brief presents a frequency compensation technique to improve the settling time in driving moderate capacitive load (10–20 pF) of a low-power (<1μW) class-AB super buffer, wherein previously reported super buffers exhibit poor stability performance. Expand
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A 2.64-$\mu \mathrm{W}$ 71-dB SNDR Discrete-Time Signal-Folding Amplifier for Reducing ADC's Resolution Requirement in Wearable ECG Acquisition Systems
TLDR
This paper presents the design of a low-power discrete-time signal-folding amplifier intended for use in place of programmable-gain amplifiers in electrocardiogram (ECG) acquisition systems. Expand
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