Woo-Yol Lee

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A 10b 205MS/S 1mm<sup>2</sup> ADC for flat-panel display applications is implemented in a 90nm CMOS process. The ADC with an LDO regulator achieves a 53dB PSRR for a 100MHz noise tone and a 55.2dB SNDR for a 30MHz 1V<sub>pp</sub> single-ended input at 205MS/S. The core ADC power consumption is 40mW from a 1V non-regulated supply.
This paper describes a 10b 204MS/s analog-to-digital converter (ADC) employing a pipelined successive approximation register (SAR) architecture for low power consumption and small area. To improve the operation frequency, the pipelined SAR ADC consists of two channels with a proposed asynchronous timing technique. This technique increases the amplification(More)
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