Wolfgang Vermeiren

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To achieve a high product quality for nano-scale systems, both realistic defect mechanisms and process variations must be taken into account. While existing approaches for variation-aware digital testing either restrict themselves to special classes of defects or assume given probability distributions to model variabilities, the proposed approach combines(More)
Based on fault simulation experiments with two microsystems, a resonant silicon beam force sensor and a miniature opto-electric transformer, this paper demonstrates the necessity to consider the interrelations between nominal system models, fault models, the construction of simulation models being capable of injecting faults, and the representation of(More)
Technology forecasts predict that nanometer IC technologies do not yield large chip areas without non-functional transistors. Mechanism of redundancy and re-organization for self-repair at the transistor and gate level are required, which can effectively handle realistic fault effects in CMOS logic circuits
Integrated circuits necessitate high quality and high yield. Defects and parameter variations are a main issue affecting both aspects. In this paper a method for characterization for statistical test is presented. The characterization is carried out for a set of digital cells using Monte Carlo fault simulation at electrical level. The results show that only(More)
Through-silicon vias (TSVs) present new, essential elements within 3D stacked Integrated Circuits (IC). Since they connect different layers of 3D stacks, their proper operation is an essential prerequisite for the system function. In this paper a procedure for deriving local digital test sequences for TSVs is presented. The behavior of TSVs including their(More)
Increasing parameter variations, high defect densities and a growing susceptibility to external noise in nanoscale technologies have led to a paradigm shift in design. Classical design strategies based on worst-case or average assumptions have been replaced by statistical design, and new robust and variation tolerant architectures have been developed. At(More)
This paper demonstrates the possibility of the occurrence of numerical problems in analogue fault simulation due to a fault-injection-caused increase of the DAE-index. Based on analytical results and fault simulation experiments with two electrical networks it is shown that a network showing no numerical problems during its fault-free simulations may(More)
1 Introduction For analogue circuits the development of automatic test generation techniques is still a subject of In this paper we propose a fault-oriented technique for generating DC-tests for nonlinear analogue circuits. At the time being the circuits to be considered have single inputs and single outputs. An extension to circuits with multiple inputs(More)
Zusammenfassung VHDL-AMS ist eine Hardwarebeschreibungssprache, mit der digitale, analoge und gemischt analogdigitale Systeme simulatorunabhängig modelliert werden können [2], [4], [11], . Der Standardisierungsprozeß der IEEE hat in diesem Jahr einen vorläufigen Abschluß erreicht. Kommerzielle Simulatoren, die VHDL-AMS-Beschreibungen zum Ausgangspunkt(More)