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In this paper we present a generic interconnect fabric for transaction level modelling tackeling three major aspects. First, a review of the bus and IO structures that we have analysed, which are common in todays system on chip environments, and require to be modelled at a transaction level. Second our findings in terms of the data structures and interface(More)
This paper gives an overview of a transaction level modeling (TLM) design flow for straightforward embedded system design with SystemC. The goal is to systematically develop both application-specific HW and SW components of an embedded system using the TLM approach, thus allowing for fast communication architecture exploration, rapid prototyping and early(More)
Early embedded SW development with transaction-level models has been broadly promoted to improve SoC design productivity. But the proposed APIs only provide low-level read/write operations via a TLM interconnect. SW developers have to implement platform-specific communication procedures and handshake protocols to access HW functions, which requires a deep(More)
We present an introspection/reflection framework for SystemC which extracts design-relevant structure information and transaction data under any LRM-2.1 compliant simulation kernel without the need for kernel modifications or a parser. The proposed methodology requires just minimal changes to the user's source code and provides an extensible interface for(More)
The system description language SystemC enables to quickly create executable specifications at adequate levels of abstraction for both hardware/software integration and fast design space exploration. Besides the modeling of a system, verification has become a dominant factor in circuit and system design. Since SystemC is a versatile language based on C++,(More)
Our concept of a virtual transaction layer (VTL) architecture allows to directly map transaction-level communication channels onto a synthesizable multiprocessor SoC implementation. The VTL is above the physical MPSoC communication architecture, acting as a hardware abstraction layer for both HW and SW components. TLM channels are represented by virtual(More)
We describe a communication-centric design methodology with SystemC that allows for efficient FPGA prototype generation of transaction level models (TLM). Using a framework comprising of well-defined communication protocols and synthesizable communication wrappers, the process of refining the TLM specification of a HW/SW system to its synthesiz-able(More)
Transaction-level modelling (TLM) is a poorly-defined term, promising a level of abstraction like RTL (register transfer level), where the key feature is a 'transaction'. But unlike registers, transactions are not well defined. While many feel they have an understanding of the term, indeed many are active proponents of this form of modelling, it remains(More)
With the emergance of ESL design methodologies, frameworks are being developed to enable engineers to easily configure and control models-under-simulation. Each of these frameworks has proven good for its specific use case, but they are incompatible. ESL engineers must be able to leverage models and tools from different sources in order to be successful.(More)