#### Filter Results:

#### Publication Year

1975

2016

#### Publication Type

#### Co-author

#### Key Phrase

#### Publication Venue

Learn More

It is shown that every deterministic multitape Turing machine of time complexity <italic>t</italic>(<italic>n</italic>) can be simulated by a deterministic Turing machine of tape complexity <italic>t</italic>(<italic>n</italic>)/log<italic>t</italic>(<italic>n</italic>). Consequently, for tape constructable <italic>t</italic>(<italic>n</italic>), the class… (More)

Realtime ray tracing has recently established itself as a possible alternative to the current rasterization approach for interactive 3D graphics. However, the performance of existing software implementations is still severely limited by today's CPUs, requiring many CPUs for achieving realtime performance.In this paper we present a prototype implementation… (More)

We show that, for multi-tape Turing machines, non-deterministic linear time is more deterministic Turing machines (that receive their input on their work tape) require time Q(n 2) to powerful than deterministic linear time. We also recognize non-palindromes of length n (it is easy to discuss the prospects for extending this result to see that time O(n log… (More)

Use of verification for testing and debugging of complex reactive systems p. 13 Experimental evaluation of FSM-based testing methods p. 23 Putting detectors in their place p. 33 Timed automata with data structures for distributed systems design and analysis p. 44 Operational semantics for real-time processes with action refinement p. 54 Specifying urgency… (More)

In the VAMP (verified architecture microprocessor) project we have designed, functionally verified, and synthesized a processor with full DLX instruction set, delayed branch, Tomasulo scheduler, maskable nested precise interrupts , pipelined fully IEEE compatible dual precision floating point unit with variable latency, and separate instruction and data… (More)

Our model of computation is a parallel computer with k synchronized processors PI,...,Pk sharing a common random access storage, where simultaneous access to the same storage location by two or more processors is not allowed. Suppose a 2-3 tree T with n leaves is implemented in the storage, suppose al,...,a k are data that may or may not be stored in the… (More)

The Verisoft project aims at the pervasive formal verification of entire computer systems. In particular, the seamless verification of the academic system is attempted. This system consists of hardware (processor and devices) on top of which runs a microkernel, an operating system, and applications. In this paper we define the computation model CVM… (More)

Asymptotically Ught tune-space trade-offs for pebblmg three d~fferent classes of directed aeychc graphs are derived Let N be the size of the graph, S the number of avadable pebbles, and T the time necessary for pebbling the graph A time-space trade-off of the form ST = O(N 2) ls proved for pebbhng (usmg only black pebbles) a specml class of permutaaon… (More)