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The Saarbr ucken Parallel Random Access Machine (SB-PRAM) is a scalable shared memory machine. At the gate level it is a re-engineered version of the Fluent machine A. G. Ranade, It uses hashing of adresses, combining and latency hiding. A prototype with 128 processors is presently being designed. In this paper we deal with several problems related to the(More)
Realtime ray tracing has recently established itself as a possible alternative to the current rasterization approach for interactive 3D graphics. However, the performance of existing software implementations is still severely limited by today's CPUs, requiring many CPUs for achieving realtime performance.In this paper we present a prototype implementation(More)
In the VAMP (verified architecture microprocessor) project we have designed, functionally verified, and synthesized a processor with full DLX instruction set, delayed branch, Tomasulo scheduler, maskable nested precise interrupts , pipelined fully IEEE compatible dual precision floating point unit with variable latency, and separate instruction and data(More)
The Verisoft project aims at the pervasive formal verification of entire computer systems. In particular, the seamless verification of the academic system is attempted. This system consists of hardware (processor and devices) on top of which runs a microkernel, an operating system, and applications. In this paper we define the computation model CVM(More)
It is shown that every deterministic multitape Turing machine of time complexity <italic>t</italic>(<italic>n</italic>) can be simulated by a deterministic Turing machine of tape complexity <italic>t</italic>(<italic>n</italic>)/log<italic>t</italic>(<italic>n</italic>). Consequently, for tape constructable <italic>t</italic>(<italic>n</italic>), the class(More)
Use of verification for testing and debugging of complex reactive systems p. 13 Experimental evaluation of FSM-based testing methods p. 23 Putting detectors in their place p. 33 Timed automata with data structures for distributed systems design and analysis p. 44 Operational semantics for real-time processes with action refinement p. 54 Specifying urgency(More)