Wolfgang E. Denzel

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The PERCS system was designed by IBM in response to a DARPA challenge that called for a high-productivity high-performance computing system. A major innovation in the PERCS design is the network that is built using Hub chips that are integrated into the compute nodes. Each Hub chip is about 580 mm in size, has over 3700 signal I/Os, and is packaged in a(More)
Since at least 1985[1] it has been known that certain traffic patterns in multistage interconnection networks, hot spots, can cause catastrophic congestion and loss of throughput. No practical technique has, until now, been demonstrated to alleviate this problem, which becomes increasingly severe as network size increases and networks are driven closer to(More)
For advanced packet switches, output queueing has received increased attention owing to its performance advantages. However, practical output queue size limitations may require additional queueing at the inputs. This paper considers a single-stage nonblocking N x N packet switch with both output and input queueing. The limited queueing at the output ports(More)
The rapid evolution in the field of telecommunications has led to the emergence of new switching technologies to support a variety of communication services with a wide range of transmission rates in a common, unified integrated services network. At the same time, the progress in the field of VSLI technology has brought up new design principles of(More)
Addressing the ever growing capacity demand for packet switches, current research focuses on scheduling algorithms or buffer bandwidth reductions. Although these topics remain relevant, our position is that the primary design focus for systems beyond 1 Tb/s must be shifted to aspects resulting from packaging disruptions. Based on trends such as increased(More)
This paper presents the architecture of a very high-speed VLSI packet switch and its performance. The switch, called PRIZMA, is suited for broadband telecommunications, based on ATM, the Asynchronous Transfer Mode. However, the concept is not restricted to ATM-oriented architectural environments. There may be applications within private networks,(More)
We present an end-to-end simulation framework that is capable of simulating High-Performance Computing (HPC) systems with hundreds of thousands of interconnected processors. The tool applies discrete event simulation and is driven by real-world application traces. We refer to it as MARS (MPI Application Replay network Simulator). It maintains reasonable(More)
Driving computer interconnection networks closer to saturation minimizes cost/performance and power consumption, but requires efficient congestion control to prevent catastrophic performance degradation during traffic peaks or “hot spot” traffic patterns. The InfiniBandTM Architecture provides such congestion control, but lacks guidance for setting its(More)
This paper presents two complementary techniques to manage the power consumption of large-scale systems with a packet-switched interconnection network. First, we propose Thrifty Interconnection Network (TIN), where the network links are activated and de-activated dynamically with little or no overhead by using inherent system events to timely trigger link(More)