Wladek Olesinski

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We describe a novel way to implement high-radix crossbar switches. Our work is enabled by a new chip interconnect technology called Proximity Communication (PxC) that offers unparalleled chip IO density. First, we show how a crossbar architecture is topologically mapped onto a PxC-enabled multi-chip module (MCM). Then, we describe a first prototype(More)
We study the problem of packet scheduling in input queued packet switches, with an emphasis on low complexity and ease of implementation. Toward this end, we propose a class of subset based schedulers, wherein an N × N switch is operated using only a small set of N configurations in every time-slot. We show that the performance of subset based scheduling is(More)
We1 propose a mechanism for providing long term quality of service in deflection networks. Our proposed protocol is in fact a call admission control (CAC) scheme based on session probing combined with a feedback technique that allows a station originating a new session to notify other stations about its bandwidth requirements. This CAC scheme works in an(More)
We introduce a simple ad-hoc routing scheme that operates in the true spirit of ad-hoc networking, i.e., in a modeless fashion, without neighborhood discovery or explicit point-to-point forwarding, while offering a high (and tunable) degree of reliability, fault-tolerance and robustness, Being aimed at truly tiny devices (e.g., with 1KB of RAM), our scheme(More)
As the number of processing nodes on chip multi-processors (CMPs) keeps increasing, providing efficient communication with the on-chip interconnect becomes increasingly critical. With 32-core CMP designs on the drawing table of engineers, there is a demand for accurate simulation models that capture all the complexities and interactions of the different(More)
In this paper, we present a flexible network on-chip topology: NR-Mesh (Nearest neighbor Mesh). The topology gives an end node the choice to inject a message through different neighboring routers, thereby reducing hop count and saving latency. At the receiver side, a message may be delivered to the end node through different routers, thus reducing hop count(More)
Large, fast switches require novel approaches to architecture and scheduling. In this paper, we propose the Output Buffered Switch with Input Groups (OBIG). We present simulation results, discuss the implementation, and show how our architecture can be used to build single-stage (flat) switches with multi-terabit-per-second throughput and hundreds of ports.(More)
We investigate experimentally the performance of de ec tion networks for jitter sensitive tra c It is a com mon belief that pure de ection networks are not suit able for isochronous applications and networks based on a connection oriented paradigm are the only solution in such cases We argue to the contrary and present simulation results supporting our(More)