Owing to rapid changes of IC technologies, traditionaldesign rule checking is becoming inadequate to assure satisfactorylevels of IC manufacturability. This paper describes a newcomputer supported design analysis environment that improvesthe efficiency of manufacturability assessment of new products.This environment, called MAPEX 2, is described in the… (More)
– A reistorless current reference source, e.g. for fast communication interfaces, has been described. Addition of currents with opposite temperature coefficient (PTC and NTC) and body effect have been used to temperature compensation. Cascode structures have been used to improve the power supply rejection ratio. The reference current source has been… (More)
This paper extends the CMOS standard cells characterization methodology for defect based testing. The proposed methodology allows to find the types of faults which may occur in a real IC, to determine their probabilities, and to find the input test vectors which detect these faults. For shorts at the inputs two types of cell simulation conditions – "… (More)
This paper describes a new algorithm for the extraction of the critical area for opens. The presented algorithm allows for the analysis of large IC's and non-Manhattan geometry. Concept of the contact/via contacting regions is proposed and its relevance is discussed. Illustrative examples of the proposed algorithm are presented.
A practical interactive tool, SENSAT, is presented for IC layout optimization based on the concept of sensitive area. Since reduction of the layout sensitivity to shorts may increase its sensitivity to opens and vice versa, a practical tool must determine sensitive areas for both. The main function of SENSAT is to extract and display the sensitive areas in… (More)
A new methodology of probabilistic analysis of CMOS physical defects in complex gates for the defect-based test is proposed. It is based on the developed approach for the identi®cation and estimation of the probability of actual faulty functions resulting from shorts caused by spot defects in conductive layers of IC layout. The aim of this methodology is… (More)
A generalized approach is presented to fault simulation and test generation based on a uniform functional fault model for different system representation levels. The fault model allows to represent the defects in components and defects in the communication network of components by the same technique. Physical defects are modeled as parameters in generalized… (More)