Wim Verhaegen

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A new technique for generating approaximate symbolic expressions for network functions in linear(ized) analog circuits is presented. It is based on the compact determinant decision diagram (DDD) representation of the circuit. An implementation of a term generation algorithm is given and its performance is compared to a matroid-based algorithm. Experimental(More)
We present a new methodology for fast analog circuit synthesis, based on the use of parameterized layout generators and symbolic performance models (SPMs) in the synthesis loop. Fast layout generation is achieved by using efficient parameterized procedural layout generators. Fast performance estimation is achieved by using pre-compiled SPMs, stored(More)
We present a layout-in-loop synthesis method for radio-frequency LNAs, which uses symbolic performance models (SPMs), parameterized layout generator and high-frequency extraction techniques in the synthesis loop. The primary focus of this work is on performance estimation using efficient SPMs and development of techniques to include layout parasitics(More)
An algorithm for the generation of tests for analog integrated circuits is proposed. It starts from a generated fault list and ranges specijied by the user and determines optimal test signals that maximize the detectability of all faults. As statistical Jluctuations have to be considered when evaluating analog circuits, it is based on a statistical test(More)
This paper presents a new method to perform efficient first-order symbolic sensitivity analysis of analog circuits by direct differentiation of symbolic expressions stored as element-coefficient diagrams (ECDs). An ECD is a compact graphical representation of a symbolic transfer function. It is the cancellation-free and per-coefficient term generation(More)
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