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Fixed-priority scheduling with deferred preemption (FPDS) has been proposed in the literature as a viable alternative to fixed-priority pre-emptive scheduling (FPPS), that obviates the need for non-trivial resource access protocols and reduces the cost of arbitrary preemptions. This paper shows that existing worst-case response time analysis of hard(More)
Outline • Context and motivation • Schedulability tests • Example • Initial values and number of iterations • Quantitative analysis • Conclusions / contributions ECRTS, July 2003 4 Context and motivation • A trend of real-time systems – Dynamics increases: many different modes that are not predictable or not known statically – High utilization required •(More)
This paper discusses improved force-directed scheduling and its application in the design of high-throughput DSP systems, such as real-time video VLSI circuits. We present a mathematical justification of the technique of force-directed scheduling, introduced by Paulin and Knight, and we show how the algorithm can be used to find cost-effective time(More)
Only very recently, single-chip MPEG2 video encoders are being reported. They are a result of additional interest in encoding in consumer products, apart from broadcast encoding, where a video encoder contains several expensive chips. Only single-chip solutions are cost-eeective enough to enable digital recording for the consumer. The professional broadcast(More)
Video processing in software is often characterized by highly fluctuating, content-dependent processing times, and a limited tolerance for deadline misses. We present an approach that allows close-to-average-case resource allocation to a single video processing task, based on asynchronous, scalable processing, and QoS adaptation. The QoS adaptation balances(More)
In this paper a multiport memory allocation problem for hierarchical, i.e. multi-dimensional, data streams is described. Memory allocation techniques are used in high level synthesis for foreground and background memory allocation, the design of data format converters, and the design of synchronous inter-processor communication hardware. The techniques(More)
P<sc>HIDEO</sc> is a silicon compiler targeted at the design of high performance real time systems with high sampling frequencies such as HDTV. It supports the complete design trajectory starting from a high level specification all the way down to layout. New techniques are used to perform global optimisations across loop boundaries in hierarchical flow(More)
Functions executed by a multi-functional processing unit (PU) correspond to clusters of operations in the specification , which are represented as Signal Flow Graphs (SFGs). Because of high-throughput demands, the operations of each SFG are executed in parallel. Since only one of the SFGs is executed at the same time, operations belonging to dtzerent SFGs(More)
We present a solution approach to the multidimensional periodic scheduling problem. We introduce the concept of multidimensional periodic operations in order to cope with problems originating from loop hierarchies and explicit timing requirements. We present an iterative algorithm for the scheduling problem, based on an ILP approach for checking the(More)