William W. Walker

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This paper evaluates and compares different clock architectures such as mesh, tree and their hybrids, on several industrial designs. The goal of our study is to gain a quantitative understanding of engineering trade-offs between different architectures with respect to clock skew, latency, timing uncertainty, and power. This understanding will lead to(More)
In this paper, we review the logical effort model presented in [1]. Based on the HSPICE simulation results using 0.18µm, CMOS technology as applied to logic blocks used in arithmetic circuits; we analyze the efficiency of the model and also present modifications that include modeling of wire delay. We propose a new model for logical effort that will better(More)
Mesh architectures are used for distributing critical global signals on a chip such as clock and power/ground. The inherent redundancy created by loops present in the mesh smooths out undesirable variations between signal nodes spatially distributed over the chip. However, one outstanding problem with mesh architectures is the difficulty in analyzing them(More)
A new Skew Tolerant Flip-Flop (STFF) that achieves the lowest reported delay and energy-delay product while absorbing up to 54ps of clock skew is described. In addition, a method for characterizing clock skew absorbing flip-flops is presented. This comparison is apples-to-apples because the best previously reported flip-flops [1-4] are fabricated on the(More)
—This paper describes the modeling of jitter in clock-and-data recovery (CDR) systems using an event-driven model that accurately includes the effects of power-supply noise, the finite bandwidth (aperture window) in the phase detector's front-end sampler, and intersymbol interference in the system's channel. These continuous-time jitter sources are captured(More)
—We present a method, on-chip test circuitry, and an error analysis, for accurate measurement of timing characteristics and power consumption of clocked storage elements. The test circuit was fabricated in 0.11 m CMOS technology and the measurements performed automatically using a serial scan interface. The precision and accuracy of the presented method are(More)
A dual-edge triggered flip-flop suitable for low power applications is presented. HSPICE simulations conducted in 0.11u CMOS technology using 1.2V power supply voltage show that the proposed design is comparable in energy-delay product to high-performance single-edge triggered flip-flops while maintaining lower clock power. The Energy-Delay Product(More)