William W. Walker

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Mesh architectures are used for distributing critical global signals on a chip such as clock and power/ground. The inherent redundancy created by loops present in the mesh smooths out undesirable variations between signal nodes spatially distributed over the chip. However, one outstanding problem with mesh architectures is the difficulty in analyzing them(More)
This paper evaluates and compares different clock architectures such as mesh, tree and their hybrids, on several industrial designs. The goal of our study is to gain a quantitative understanding of engineering trade-offs between different architectures with respect to clock skew, latency, timing uncertainty, and power. This understanding will lead to(More)
We present a method, on-chip test circuitry, and an error analysis, for accurate measurement of timing characteristics and power consumption of clocked storage elements. The test circuit was fabricated in 0.11 m CMOS technology and the measurements performed automatically using a serial scan interface. The precision and accuracy of the presented method are(More)
A new Skew Tolerant Flip-Flop (STFF) that achieves the lowest reported delay and energy-delay product while absorbing up to 54ps of clock skew is described. In addition, a method for characterizing clock skew absorbing flip-flops is presented. This comparison is apples-to-apples because the best previously reported flip-flops [1-4] are fabricated on the(More)
We present a leakage current replica (LCR) keeper for dynamic domino gates that uses an analog current mirror to replicate the leakage current of a dynamic gate pull-down stack and thus tracks process, voltage, and temperature. The proposed keeper has an overhead of one field-effect transistor per gate plus a portion of a shared current mirror. Techniques(More)
A dual-edge triggered flip-flop suitable for low power applications is presented. HSPICE simulations conducted in 0.11u CMOS technology using 1.2V power supply voltage show that the proposed design is comparable in energy-delay product to highperformance single-edge triggered flip-flops while maintaining lower clock power. The Energy-Delay Product(More)
An immunohistochemical assay for proliferating cell nuclear antigen (PCNA) identifies cells in all active phases of the cell cycle. In this study, PCNA methodology, which was developed primarily for mammalian tissues, was adapted to three small fish species, medaka (Oryzias latipes), guppy (Poecilia reticulata), and western mosquitofish (Gambusia affinis)(More)
A hybrid CDR is presented that embeds a 5 blind-oversampling CDR within a conventional phase-tracking CDR. This hybrid CDR has a jitter tolerance that is the product of the individual jitter tolerances. In this implementation, the jitter tolerance of a phase-tracking CDR alone is increased by a factor of 32 at frequencies below its loop filter’s bandwidth,(More)