Learn More
In this paper the benefits of implementation of the Tate pair-ing computation in dedicated hardware are discussed. The main observation lies in the fact that arithmetic architectures in the extension field GF (3 6m) are good candidates for parallelization, leading to a similar calculation time in hardware as for operations over the base field GF (3 m).(More)
This paper presents an energy-efficient medium access control protocol suitable for communication in a wireless body area network for remote monitoring of physiological signals such as EEG and ECG. The protocol takes advantage of the static nature of the body area network to implement the effective time-division multiple access (TDMA) strategy with very(More)
Adaptive probabilistic modeling of the EEG background is proposed for seizure detection in neonates with hypoxic ischemic encephalopathy. The decision is made based on the temporal derivative of the seizure probability with respect to the adaptively modeled level of background activity. The robustness of the system to long duration "seizure-like" artifacts,(More)
There has been a lot of interest in recent years in the problems faced by cryptosystems due to side channel attacks. Algorithms for elliptic curve point scalar multiplication such as the double-and-add method are prone to such attacks. By making use of special addition chains, it is possible to implement a Simple Power Analysis (SPA) resistant cryptosystem.(More)
OBJECTIVE The objective of this study was to validate the performance of a seizure detection algorithm (SDA) developed by our group, on previously unseen, prolonged, unedited EEG recordings from 70 babies from 2 centres. METHODS EEGs of 70 babies (35 seizure, 35 non-seizure) were annotated for seizures by experts as the gold standard. The SDA was tested(More)
This paper presents a review of some existing architectures for the implementation of Montgomery modular multiplication and exponentiation on FPGA (<i>Field Programmable Gate Array</i>). Some new architectures are presented, including a pipelined architecture exploiting the maximum carry chain length of the FPGA which is used to implement the modular(More)