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This paper discusses the implementation of a random logic function on an array of CMOS transistors. A graph-theoretical algorithm which minimizes the size of an array is presented.
New placement algorithms have been developed which are suitable for the layout of Very Large Scale Integrated (VLSI) circuits Hierarchical decomposition is used to reduce the circuit function to a size that can be comprehended by the designer and is computationally feasible to layout. At each hierarchical level the problem consists of the placement of… (More)
Although design languages have been in existence since the early 1960's, only in the last few years has there been a concerted effort to bring them into the design process as a useful tool. The major applications of design languages are: 1. Description of the behavior and/or structure of a system as a means for accurately communicating design details… (More)
In this report a language (SDL) for describing structural properties of digital systems will be presented. SDL can be used at all levels of the design process i. e. from the system level down to the circuit level. The language is intended as a complement to existing computer hardware description languages, which emphasize behavioural description.The… (More)
Bit maps have been used in many Design Automation (DA) algorithms such as printed circuit board (PCB) layout and integrated circuit (IC) design rule checking (DRC). The attraction of bit maps is that they provide a direct representation of two-dimensional images. The difficulty with large scale use of bit maps (e.g., for DRC on VLSI) is that the large… (More)
SABLE (Structure And Behavior Linking Environment) is a system currently being developed at Stanford to support structured, multi-level behavior specification and simulation of digital systems. SABLE accepts information about the nesting and interconnectivity of components, and combines it with descriptions of their behavior, which are written in a new… (More)
This paper describes an automatic PLA synthesis (APLAS) system which automatically generates a PLA for the control function of a design from a DDL-P description of a digital system. APLAS can also minimize and partition the PLA to meet the design constraints. This is a very convenient tool for designing finite state machines. The control circuit of any… (More)
This paper reviews recent developments in the verification of digital systems designs. The emphasis is on proof of functional correctness. Some of the techniques reviewed are symbolic simulation (including parallel simulation of HDL descriptions), dataflow verification by grammar construction, comparison of manually generated design with automated design,… (More)
The use of topological methods for the circuit layout problem is surveyed first. In the second part an improved model is proposed, which allows pin and gate assignment in function of the layout.
This paper describes a heuristic algorithm for automatically partitioning digital systems. High level information contained within a hierarchical design is used to increase the effectiveness of this algorithm. This algorithm uses a constructive process to build a physical design of a hierarchically specified logic design. An iterative improvement step is… (More)