William M. van Cleemput

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Bit maps have been used in many Design Automation (DA) algorithms such as printed circuit board (PCB) layout and integrated circuit (IC) design rule checking (DRC). The attraction of bit maps is that they provide a direct representation of two-dimensional images. The difficulty with large scale use of bit maps (e.g., for DRC on VLSI) is that the large(More)
In this report a language (SDL) for describing structural properties of digital systems will be presented. SDL can be used at all levels of the design process i. e. from the system level down to the circuit level. The language is intended as a complement to existing computer hardware description languages, which emphasize behavioural description.The(More)
SABLE (Structure And Behavior Linking Environment) is a system currently being developed at Stanford to support structured, multi-level behavior specification and simulation of digital systems. SABLE accepts information about the nesting and interconnectivity of components, and combines it with descriptions of their behavior, which are written in a new(More)
This paper describes the implementation and performance of SPRINT, an interactive system for printed circuit board design developed at the Stanford Linear Accelerator Center (SLAC). Topics discussed include the placement subsystem, the routing subsystem consisting of an interactive manual router, an automatic batch router, and a via elimination program, as(More)
This paper describes a heuristic algorithm for automatically partitioning digital systems. High level information contained within a hierarchical design is used to increase the effectiveness of this algorithm. This algorithm uses a constructive process to build a physical design of a hierarchically specified logic design. An iterative improvement step is(More)
This paper reviews recent developments in the verification of digital systems designs. The emphasis is on proof of functional correctness. Some of the techniques reviewed are symbolic simulation (including parallel simulation of HDL descriptions), dataflow verification by grammar construction, comparison of manually generated design with automated design,(More)