William Keshlear

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In a previous issue, we described a study of translation buffer performance undertaken in conjunction with the design of a memory management unit for a new 32 bit microprocessor [Alex85b]. This work produced generalized results via trace-driven simulations. The address reference traces were obtained from typical multitasking UNIX workloads and have now been(More)
Durin9 the design of i memory menagement unK for a new 32 bit microprocessor (32 bit address & data), we were confounded by the lack of general & credible trenslaUon buffer (TB) performance evaluations. That led Lo this study, which we hope can benefit other designers. Although our evaluaUon is from s 32 bit, VLSI, and UNIX" perspective, mosL results r e(More)
This paper describes the methodology and tools used to drive static and dynamic power savings while significantly improving the operating frequency of a 45 nm custom x86-64 processor core used in several multi-core devices. The power improvements were essential for future six-, eight-, and twelve-core server processors, but notable improvements have already(More)
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