William Ellersick

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— In this paper, we present the Tiny Tera: a small packet switch with an aggregate bandwidth of 320Gb/s. The Tiny Tera is a CMOS-based input-queued, fixed-size packet switch suitable for a wide range of applications such as a high-performance ATM switch, the core of an Internet router or as a fast multiprocessor interconnect. Using off-the-shelf technology,(More)
—This paper presents a transceiver that uses a 4-bit flash analog-to-digital converter (ADC) for the receiver and an 8-bit current-steering digital-to-analog converter (DAC) for the transmitter. The 8-GSamples/s converters are 8-way time inter-leaved. Digital compensation reduces the input offset of the ADC comparators to less than 0.6 LSB, improves the(More)
The long links that interconnect networking and computing systems and boards need high throughput to avoid expensive, massively parallel connections. However, long wires suffer signal losses that increase with frequency. Digital communication techniques can compensate for these losses, but require Analog-to-Digital and Digital-to-Analog converters (ADCs and(More)
— This paper describes the design of a novel CMOS 2 Gb/s asymmetric serial link. The serial link is designed for systems that use high speed chip-to-chip communications. In such designs, power dissipation is a common problem, particularly when multiple serial links are required on one chip. The power arises primarily from the phase adjustment circuitry used(More)
We report on the design and testing of a custom application-specific integrated circuit (ASIC) that has been developed as a key component of the Boston retinal prosthesis. This device has been designed for patients who are blind due to age-related macular degeneration or retinitis pigmentosa. Key safety and communication features of the low-power ASIC are(More)
— This paper presents a transceiver that uses a 4-bit flash ADC for the receiver and an 8-bit current-steering DAC for the transmitter. The 8-GSa/s converters are 8-way time interleaved. Digital compensation reduces the input offset of the ADC comparators to less than 0.6LSB, improves the accuracy of the interleaved sampling clocks to within 10ps, and(More)
  • Nick Mckeown, Martin Izzard, Adisak Mekkittikul, William Ellersick, Mark Horowitz
  • 1996
— In this paper, we present the Tiny Tera: a small packet switch with an aggregate bandwidth of 320Gb/s. The Tiny Tera is a CMOS-based input-queued, fixed-size packet switch suitable for a wide range of applications such as a high-performance ATM switch, the core of an Internet router or as a fast multiprocessor interconnect. Using off-the-shelf technology,(More)
  • Kun-Yung Ken Chang, William Ellersick, Shang-Tse Chuang, Stefanos Sidiropoulos, Mark Horowitz
  • 1998
The design of an asymmetric serial link poses a number of trade-offs for the designer. This paper describes measurements from a 0.25µm CMOS test chip which show that a properly designed asymmetric link can achieve 2Gb/s using single-ended signalling with a bit-error rate < 10-14. Architecture Using high-speed serial links in network switches can provide(More)
A hermetic neurostimulator is being developed to restore functional sight to the blind. The latest developments are presented on the Boston 256-channel retinal prosthesis. The device includes a hermetic package made of titanium and alumina, containing an integrated circuit chip with 256 independently addressable current drivers. The prosthesis attaches to(More)