William E. Dougherty

Learn More
Routability or wiring congestion in a VLSI chip is becoming increasingly important as chip complexity increases. Congestion has a significant impact on performance, yield and chip area. Although advances in placement algorithms have attempted to alleviate this problem, the inherent structure of the logic netlist has a significant impact on the routability(More)
Systems-on-chip (SoC) continue to be very complex to design and verify, despite extensive component reuse. Although reusable components are pre-designed and pre-verified, when they are assembled in an SoC there is no guarantee that the whole system will behave as expected from a performance, cost and integration point of view. In many cases this is because(More)
Power consumption is an increasingly important consideration in the design of mixed hardware/software systems. This work defines the notion of instruction subsetting and explores its use as a means of reducing power consumption from the system level of design. Instruction subsetting is defined as creating an application specific instruction set processor(More)
GOALS System level design involves a series of tradeoffs in determining the best way to implement a particular task in the hardware/software design space. ASIC implementations can be optimized for a variety of parameters including execution speed, throughput, or power consumption , but do not offer any flexibility as far as future applications are(More)
While guarded evaluation has proven an effective energy saving technique in arithmetic circuits, good methodologies do not exist for determining when and how to guard for maximal savings. Three new internal guarding techniques are presented in adders that increase energy savings up to 38% over existing external guarding techniques. This allows guarded(More)
Genetic algorithms have proven to be a viable solution to the NP-complete problem of test vector generation. However , the parameters used to control GA-based ATPG can greatly affect test set size, fault coverage, and CPU execution time. Knowing how a given set of parameters will affect each of these factors a priori allows for more efficient testing(More)
  • 1