William B. Toms

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m-of-n codes can be used for carrying data over selftimed on-chip interconnect links. Such codes can be chosen to have low redundancy, but the costs of encoding/decoding data is high. The key to enabling the cost-effective use of m-of-n codes is to find a suitable mapping of the binary data to the code. This paper presents a new method for selecting(More)
A novel concept of logic redundancy insertion is presented that facilitates significant latency reduction in self-timed adder circuits. The proposed concept is universal in the sense that it can be extended to a variety of self-timed design methods. Redundant logic can be incorporated to generate efficient self-timed realizations of iterative logic(More)
Speed-Independent synthesis of combinational logic datapath circuits using tools such as Petrify is often inefficient or infeasible because such circuits typically contain many concurrent inputs and independent outputs. This paper presents a practical method for generating arbitrary combinational logic circuits, using a sub-class of speed-independent(More)
Self-timed circuits present an attractive solution to the problem of process variation. However, implementing selftimed combinational logic is complex and expensive. This paper presents a novel method for synthesising indicating implementations of arbitrary encoded function blocks. The synthesis method reduces the cost of the implementations by distributing(More)
Self-timed datapaths require their data to be encoded in a delay-insensitive manner. The dual-rail encoding is commonly used, but more complex codes offer the possibility of better energy efficiency or fewer wires-per-bit. However, these advantages are often negated by datapath manipulations within large systems that require code-groups to be split and(More)
Implementing combinational logic efficiently in QDI designs is hard, due to the need to acknowledge every transition, and naive approaches are often used. The paper demonstrates the problem of using Delay-Insensitive Minterm Synthesis on anything but the smallest designs.These problems can be overcome by employing techniques from MultiLevel Logic synthesis.(More)