Wilhelmus A. M. Van Noije

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The implementation of a dual-modulus prescaler (divide by 128/129) using an extension of the true-single-phase-clock (TSPC) technique, the extended TSPC (E-TSPC), is presented. The E-TSPC [1], [2] consists of a set of composition rules for single-phase-clock circuits employing static, dynamic, latch, dataprecharged, and NMOS-like CMOS blocks. The(More)
New structures to be applied with the extended truesingle-phase-clock (E-TSPC) CMOS circuit technique, an extension of the traditional true-single-phase-clock (TSPC) [1], [2], are presented. These structures, formed by the connection of proper data paths, allow circuits to handle data with rates that are twice the clock rate. Examples of circuits employing(More)
The design of a dual modulus prescaler 32/33 in a 0.35μm CMOS technology is presented. The prescaler is a circuit employed in high frequency synthesizer designs. In the proposed circuit the technique called Extended True Single Phase Clock (E-TSPC), an extension of the True Single Phase Clock (TSPC) technique, was applied. Additionally some new(More)
This paper presents an improved methodology to automate the design and minimize the power consumption of typical CMOS OTAs. Using a geometric program formulation, this methodology can handle simultaneously several performance specifications including quiescent power, DC gain, unity-gain bandwidth, CMRR and phase margin among others. We present some(More)
We propose the definition and evaluation of an instruction set designed and tuned for multimedia applications on a Digital Set-Top-Box. The proposed instruction set had its performance evaluated in software and hardware to obtain the best cost / benefit relationship referring to performance and silicon chip area. An instruction set was obtained enhancing(More)
A simplified voltage reference topology with low power consumption based on MOS transistors in weak inversion operation is presented. A 176 <i>mV</i> @ 27&#176;<i>C</i> output voltage with a quiescent current of 2.7 &#956;<i>A</i> @ 3.3 <i>V</i> and a thermal coefficient of 8.8 &#956;<i>V/&#176;C</i> in the temperature range of [-25; 100] &#176;<i>C</i> had(More)
The design of a dual modulus prescaler 32/33 in a 0.35 &#181;m CMOS technology is presented. In the circuit the technique called Extended True Single Phase Clock (E-TSPC) was applied. Additionally, some dedicated structures to double the data output rate were also employed. The prescaler was implemented and tested and experimental results indicated that the(More)
The implementation of a four bits programmable high speed frequency divider for a Frequency Synthesizer, using a 0.35 &#956;m CMOS technology, is described. The programmable divider employs a divide-by-32/33 dual-modulus prescaler, two other counters, and the logic control necessary to operate the division. Additionally, a complete 2.4 GHz Synthesizer was(More)