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Recent changes in CMOS device structures and materials motivated by impending atomistic and quantum-mechanical limitations have profoundly influenced the nature of delay and power variability. Variations in process, temperature, power supply, wear-out, and use history continue to strongly influence delay. The manner in which tolerance is specified and(More)
Although carbon nanotube (CNT) transistors have been promoted for years as a replacement for silicon technology, there is limited theoretical work and no experimental reports on how nanotubes will perform at sub-10 nm channel lengths. In this manuscript, we demonstrate the first sub-10 nm CNT transistor, which is shown to outperform the best competing(More)
An eightfold improvement in power efficiency can be achieved without loss of performance for modestly parallelizable CMOS-based computer systems. ABSTRACT | After decades of continuous scaling, further advancement of silicon microelectronics across the entire spectrum of computing applications is today limited by power dissipation. While the trade-off(More)
Despite generation upon generation of scaling, computer chips have until now remained essentially 2-dimensional. Improvements in on-chip wire delay and in the maximum number of I/O per chip have not been able to keep up with transistor performance growth; it has become steadily harder to hide the discrepancy. 3D chip technologies come in a number of(More)
To a large extent, scaling was not seriously challenged in the past. However, a closer look reveals that early signs of scaling limits were seen in high-performance devices in recent technology nodes. To obtain the projected performance gain of 30% per generation, device designers have been forced to relax the device subthreshold leakage continuously from(More)
Energy efficiency has become a ubiquitous design requirement for digital circuits. Aggressive supply-voltage scaling has emerged as the most effective way to reduce energy use. In this work, we review circuit behavior at low voltages, specifically in the subthreshold (V dd , V th) regime, and suggest new strategies for energy-efficient design. We begin with(More)
The purpose of this study was to explore whether there is a linkage between the infiltration of CD8(+) T cells and the risk of death from esophageal cancer. Cases of 70 consecutive patients in whom esophageal squamous cell carcinomas ( n = 33) or adenocarcinomas (n = 37) were R0-resected between 1993 and 1999 were reviewed. The presence of activated CD8(+)(More)
The first sub-100nm technology that allows the monolithic integration of optical modulators and germanium photodetectors as features into a current 90nm base high-performance logic technology node is demonstrated. The resulting 90nm CMOS-integrated Nano-Photonics technology node is optimized for analog functionality to yield power-efficient single-die(More)