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This chapter introduces Chess, a retargetable code generation environment for xed-point DSP processors. Chess addresses a range of commercial as well as application-speciic processors, which are increasingly being used for embedded applications in telecommunications, speech and audio processing. Chess is based on a mixed be-havioural/structural processor(More)
The goal of this paper is to extend the synthesis of real time digital signal processing (DSP) algorithms towards the domain of high throughput applications. A novel architectural style specitlcally suited for this application domain is presented. Furthermore, a synopsis of a novel synthesis script typically oriented towards this architecture is described(More)
The increasing use of embedded software, often implemented on a core processor in a single-chip system, is a clear trend in the telecommunications, multi-media and consumer electronics industry. A companion paper in this issue [1] presents a survey of application and architecture trends for embedded systems in these growth markets. However, the lack of(More)
Embedded processors in electronic systems typically are tuned to a few applications. Development of processor specific compilers is prohibitively expensive and as a result such compilers, if existing, yield code of an unacceptable quality. To improve this code quality, we developed a retargetable and optimising code generator. It uses a graph based(More)
Many real-time signal processing applications are dominated by iterative loop constructs which exhibit a large amount of parallelism. In general, a realisation matched to the required rate of these applications exploits only a relatively small part of the parallelism available in the algorithm. This paper addresses the important problem of selecting the(More)
In thispapec a novel technique for the synthesis of complex multi-functional units is presented. Given a set of jimctions or instructions, the goal is to minimise the area cost of a unit that can execute these functions. A common set ofprimitivefunctional units is allocated and shared between operations which belong to different functions. In the presented(More)
In this paper, a technique for the allocation of complex application specific datapaihs will be presented. The technique is especially suited for the synthesis of application specijic architectures for high-throughput signal processing applications. Such applications comprise hierarchical compositions of nested loops and condition blocks. A minimum area set(More)
Embedded processors in electronic systems typically are tuned to a few applications. Development of processor-specific compilers is prohibitively expensive and, as a result, such compilers, if existing, yield code of an unacceptable quality. To improve this code quality, we developed a processor model that captures the connectivity, the parallelism, and all(More)
— SoCs will soon have to integrate tens of complex system functions, each with their own optimal balance of performance, flexibility, energy consumption, communication, and design time. The traditional model of a (configurable) general-purpose processor core with a number of hardware accelerators no longer suffices. Application-specific instruction-set(More)