Wenjun Sheng

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—A fully integrated CMOS low-IF Bluetooth receiver is presented. The receiver consists of a radio frequency (RF) front end, a phase-locked loop (PLL), an active complex filter, a Gaussian frequency shift keying (GFSK) demodulator, and a frequency offset cancellation circuit. The highlights of the receiver include a low-power active complex filter with a(More)
—A unified system-level design methodology for highly integrated CMOS radio frequency receiver design is introduced. This complete system-level design methodology is targeted to minimize the total power consumption of the receiver. System-level design techniques which can be used to derive the overall receiver radio specifications and study noise and(More)
—An efficient mixed-mode Gaussian frequency-shift keying (GFSK) demodulator with a frequency offset cancellation circuit is presented. The structure is suitable for a low-IF Blue-tooth receiver and can also be applied to other receivers involving continuous phase shift keying (CPSK) signals. The demodulator implementation is robust to tolerate process(More)
This first commercially available CMOS CDMA transmitter IC is based on a zero-IF architecture and designed for US/China/Korea and Japan cellular bands. The transmitter IC integrates direct upconverter, VGA, driver amplifier, VCO, and both transmit and receive PLLs in 0.24 /spl mu/m CMOS. The chip provides more than 100 dB power control range and consumes(More)
In this work, we investigate the controlled fabrication of Sn-doped TiO2 nanorods (Sn/TiO2 NRs) for photoelectrochemical water splitting. Sn is incorporated into the rutile TiO2 nanorods with Sn/Ti molar ratios ranging from 0% to 3% by a simple solvothermal synthesis method. The obtained Sn/TiO2 NRs are single crystalline with a rutile structure. The(More)
This paper presents a monolithic low-IF Bluetooth receiver. The highlights of the receiver include a low-power active complex filter with a non-conventional tuning scheme and a high performance mixed-mode GFSK demodulator. The chip was fabricated on a 6.25 mm/sup 2/ die using TSMC 0.35 /spl mu/m standard CMOS process. -82 dBm sensitivity at 1e-3 BER, -10(More)
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