Wen-Kuan Yeh

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Article history: Received 12 November 2010 Received in revised form 14 December 2010 Accepted 28 December 2010 Available online 17 January 2011 0026-2714/$ see front matter 2010 Elsevier Ltd. A doi:10.1016/j.microrel.2010.12.015 ⇑ Corresponding author. Tel.: +1 407 8235719; fax: E-mail address: yuanj@mail.ucf.edu (J.-S. Yuan). Negative-bias temperature(More)
Vertical hot electron transistors incorporating atomically-thin 2D materials, such as graphene or MoS2, in the base region have been proposed and demonstrated in the development of electronic and optoelectronic applications. To the best of our knowledge, all previous 2D material-base hot electron transistors only considered applying a positive(More)
The experimental observation of band-to-band tunneling in novel tunneling field-effect transistors utilizing a monolayer of MoS2 as the conducting channel is demonstrated. Our results indicate that the strong gate-coupling efficiency enabled by two-dimensional materials, such as monolayer MoS2 , results in the direct manifestation of a band-to-band(More)
Article history: Received 23 November 2009 Received in revised form 21 January 2010 Available online 1 March 2010 0026-2714/$ see front matter 2010 Elsevier Ltd. A doi:10.1016/j.microrel.2010.01.045 * Corresponding author. E-mail address: ykfang@ee.ncku.edu.tw (Y.-K. Fang In this work, influences of oxygen effect on an Hf-based high-k gate dielectric were(More)
This letter investigates hot-carrier-induced degradation on 0.1 m partially depleted silicon-on-insulator (SOI) nMOSFETs at various ambient temperatures. The thermal impact on device degradation was investigated with respect to body-contact nMOSFETs (BC-SOI) and floating-body SOI nMOSFETs (FB-SOI). Experimental results show that hot-carrier-induced(More)
The effect of post-thermal annealing (PA) after halo implantation on the reliability of sub-0.1 /spl mu/m CMOSFETs was investigated. We found that the control of annealing time is more efficient than that of annealing temperature with respect to improving the hot-carrier-induced device degradation. The best results of device performance were obtained with(More)
This study investigates the effects of oxide traps induced by SOI of various thicknesses (TSOI = 50, 70 and 90 nm) on the device performance and gate oxide TDDB reliability of Ni fully silicide metal-gate strained SOI MOSFETs capped with different stressed SiN contact-etch-stop-layer (CESL). The effects of different stress CESLs on the gate leakage currents(More)
High-frequency operation with ultrathin, lightweight, and extremely flexible semiconducting electronics is highly desirable for the development of mobile devices, wearable electronic systems, and defense technologies. In this work, the experimental observation of quasi-heterojunction bipolar transistors utilizing a monolayer of the lateral WSe2-MoS2(More)