Wen-Jong Fang

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<italic>This paper presents a new performance-driven partitioning method for multi-FPGA designs. The proposed method consists of three steps: (1) functional-cluster formation, (2) slack computation, and (3) set-covering-based partitioning with functional replication. The proposed method performs multi-FPGA partitioning by taking into account path delays and(More)
In this paper, we present a new synthesis and partitioning approach for multiple-FPGA implementations from Register-Transfer-Level (RTL) netlists. Our approach bridges the gap between RTL/logic synthesis and physical partitioning by finely tuning logic implementations suited for multiple-FPGA systems. We propose a hierarchical functional structuring and(More)
In this paper, we present a new integrated synthesisand partitioning method for multiple-FPGA applications.This method first synthesizes a design specificationin a fine-grained way so that functional clusters can bepreserved based on the structural nature of the designspecification.Then, it applies a hierarchical set-coveringpartitioning method to form the(More)
We propose an integrated HDL-synthesis and placement method for row-based layouts. Our approach bridges the gap between HDL synthesis and placement by fully utilizing design hierarchy. It jkt synthesizes an HDL design specification into a hierarchy of subcir-cuits. It then groups subcircuits to form strongly connected macro cells, followed by performing a(More)
In recent years, logic emulation has been widely usedas a key design verification methodology in many complex CPU, telecom, and multimedia design projects. When using logic emulation for design verification, designers often need toperform engineering changes as a result of design debugging of a design specificationmodification. One of the essential issues(More)
Logic emulation is a technique that uses dynamically reprogrammable systems for prototyping and design verification. Using an emulator, designers can realize designs through a software configuration process and perform real-time design verification before fabricating the chip into silicon. However, converting designs into an emulator involves the use of(More)
Converting an HDL-based design into an emulation system for design veriication is an extremely complex and time-consuming task. One possible solution to improve productivity is an eeective e m ulation-based design methodology that exploits the modularity of designs. This paper develops and explores such a methodology. We present a m ulti-level synthesis(More)
This paper presents a datapath generator for multiple-FPGA applications. This datapath generator is able to generate complex datapath designs described in HDLs. Our datapath generator uses a novel synthesis and partitioning approach which bridges the gap between RTLLlogic synthesis and physical partitioning to fully exploit design structural hierarchy for(More)