Wen-Hann Wang

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We propose and analyze a two-level cache organization that provides high memory bandwidth. The first-level cache is accessed directly by virtual addresses. It is small, fast, and, without the burden of address translation, can easily be optimized to match the processor speed. The virtually-addressed cache is backed up by a large physically-addressed cache;(More)
We propose improvements to current trace-driven cache simulation methods to make them faster and more economical. We attack the large time and space demands of cache simulation in two ways. First, we reduce the program traces to the extent that exact performance can still be obtained from the reduced traces. Second, we devise an algorithm that can produce(More)
In this paper we argue that a two-way second-level cache is a better design choice than a direct-mapped organization. We show two-way caches are as simple to implement as direct-mapped caches. If the cache controller contains tags, the data array can be organized as a single bank of standard SRAM. Otherwise, both tags and data can be organized as a single(More)