Wen-Chien Su

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The trend towards heterogeneous multi-core integration and higher communication bandwidth drastically increases the complexity of the SoC. Architecture design and system validation become extremely challenging. This paper presents a system-level virtual platform and simulation environment for multi-core system performance profiling and evaluation. At the(More)
Two approaches for parallelization of H.264 decoder, data partition and function partition, are realized on a PAC Duo platform, which contains two Parallel Architecture Core Digital Signal Processors (PACDSP's). Eight baseline CIF sequences are decoded and their execution cycles and waiting cycles are examined. There are three roots hindering the(More)
H.264 has become a popular video compression standard for years; however, the complexity of computation and huge amount of external data access are still the main problems. In this paper, we will propose two mechanisms to fulfill high performance H.264 baseline profile decoder on PAC Duo SOC platform. To reduce the complexity of computation, in addition to(More)
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