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A New Design of In-Memory File System Based on File Virtual Address Framework
TLDR
This paper presents a framework based on a new concept, “File Virtual Address Space”. Expand
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Accuracy vs. Efficiency: Achieving Both through FPGA-Implementation Aware Neural Architecture Search
TLDR
We use Field Programmable Gate Arrays (FPGAs) as a vehicle to present a novel hardware-aware NAS framework, namely FNAS, which will provide an optimal neural architecture with latency guaranteed to meet the specification. Expand
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Heterogeneous FPGA-Based Cost-Optimal Design for Timing-Constrained CNNs
TLDR
In this paper, we explore heterogeneous FPGA-based designs to effectively leverage both task and data parallelism, such that the resultant system can achieve the minimum cost while satisfying timing constraints. Expand
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Optimizing data placement for reducing shift operations on Domain Wall Memories
TLDR
We present an efficient heuristic, called Grouping-Based Data Placement (GBDP), for the data placement problem of a given data access sequence on DWM. Expand
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Efficient Data Placement for Improving Data Access Performance on Domain-Wall Memory
TLDR
A domain-wall memory (DWM) is becoming an attractive candidate to replace the traditional memories for its high density, low-power leakage, and low access latency. Expand
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Achieving Super-Linear Speedup across Multi-FPGA for Real-Time DNN Inference
TLDR
We employ multiple FPGAs to cooperatively run DNNs with the objective of achieving super-linear speed-up against single-FPGA design. Expand
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FoToNoC: A Folded Torus-Like Network-on-Chip Based Many-Core Systems-on-Chip in the Dark Silicon Era
TLDR
We present FoToNoC, a Folded Torus-like NoC, coupled with a hierarchical management strategy for heterogeneous many-core systems. Expand
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On Neural Architecture Search for Resource-Constrained Hardware Platforms
TLDR
We propose a new framework to jointly explore the space of neural architecture, hardware implementation, and quantization. Expand
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Designing an efficient persistent in-memory file system
TLDR
A new design of persistent, in-memory file system on persistent memory attached to memory bus based on the novel framework of file virtual address space. Expand
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XFER: A Novel Design to Achieve Super-Linear Performance on Multiple FPGAs for Real-Time AI
TLDR
We leverage a cluster of FPGAs to fully exploit the parallelism in DNNs with the objective of obtaining super-linear performance. Expand
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