A standard cell library typically contains several versions of any given gate type, each of which has a di erent gate size. We consider the problem of choosing optimal gate sizes from the library toâ€¦ (More)

The problem of power-delay tradeoffs in transistor sizing is examined using a nonlinear optimization formulation. Both the dynamic and the short-circuit power are considered, and a new modelingâ€¦ (More)

This paper examines the problem of minimizing the area of a synchronous sequential circuit for a given clock period specification under the standard-cell paradigm. This is effected by appropriatelyâ€¦ (More)

This paper examines the problem of minimizing the area of a synchronous sequential circuit for a given clock period speci cation under the standard-cell paradigm. This is e ected by appropriatelyâ€¦ (More)

Abstract: The problem of sizing gates for power-delay tradeoffs is of great interest to designers. In this work, the theoretical basis for gate sizing under delay and power considerations isâ€¦ (More)

A three-step algorithm is presented for discrete gate sizing problem of delay/area optimization under double-sided timing constraints. The problem is rst formulated as a linear program. The solutionâ€¦ (More)

In this paper, we first present an efficient algorithm for the gate sizing problem. Then we propose an algorithm which performs delay and area optimization for a given compact placement by resizingâ€¦ (More)

The problem of sizing gates for power-delay tradeo s is of great interest to designers. In this work, the theoretical basis for gate sizing under delay and power considerations is presented, andâ€¦ (More)

AbstructA standard cell library typically contains several versions of any given gate type, each of which has a different gate size. We consider the problem of choosing optimal gate sizes from theâ€¦ (More)