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—Packet classification is a fundamental enabling function for various applications in switches, routers and firewalls. Due to their performance and scalability limitations, current packet classification solutions are insufficient in addressing the challenges from the growing network bandwidth and the increasing number of new applications. This paper(More)
Most high-speed Internet Protocol (IP) lookup implementations use tree traversal and pipelining. However, this approach results in inefficient memory utilization. Due to available on-chip memory and pin limitations of FPGAs, state-of-the-art designs on FPGAs cannot support large routing tables arising in backbone routers. Therefore, ternary content(More)
Continuous growth in network link rates poses a strong demand on high speed IP lookup engines. While Ternary Content Addressable Memory (TCAM) based solutions serve most of today's high-end routers, they do not scale well for the next-generation. On the other hand, pipelined SRAM- based algorithmic solutions become attractive. Intuitively multiple pipelines(More)
Pipelined SRAM-based algorithmic solutions have become competitive alternatives to TCAMs (ternary content addressable memories) for high throughput IP lookup. Multiple pipelines can be utilized in parallel to improve the throughput further. However, several challenges must be addressed to make such solutions feasible. First, the memory distribution over(More)
Routing metrics play a critical role in wireless mesh networks (WMNs). Several metrics have already been proposed but none of them can well meet the specific requirement brought by large-scale multi-radio mesh networks (LSMRMNs). In LSMRMNs, most of traffic has much longer paths than in small scale WMNs. The channel distribution on a long path thus has a(More)
Vehicular Ad hoc Network (VANET) is a special class of wireless mobile communication network. For vehicle-to-vehicle (V2V) communication, suitable routing protocols are needed. A routing metric combining hop counts and retransmission counts at MAC layer is proposed with consideration of link quality and delay reduction. Based on the new routing metric, a(More)
In this paper we present a novel architecture for high-speed and high-capacity <i>regular expression matching</i> (REM) on FPGA. The proposed REM architecture, based on nondeterministic finite automaton (RE-NFA), efficiently constructs <i>regular expression matching engines</i> (REME) of arbitrary regular patterns and character classes in a uniform(More)
—Multi-field packet classification has evolved from traditional fixed 5-tuple matching to flexible matching with arbitrary combination of numerous packet header fields. For example, the recently proposed OpenFlow switching requires classifying each packet using up to 12-tuple packet header fields. It has become a great challenge to develop scalable(More)
Rapid growth in network link rates poses a strong demand on high speed IP lookup engines. Trie-based architec-tures are natural candidates for pipelined implementation to provide high throughput. However, simply mapping a trie level onto a pipeline stage results in unbalanced memory distribution over different stages. To address this problem, several novel(More)