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Dynamic reconfiguration for fine-grained architectures is still associated with significant reconfiguration costs. In this paper, a new placement algorithm is proposed to reduce the size of FPGA reconfiguration bitstream. The algorithm is modified on the existing placement algorithm within VPR. It introduces the CLBs configuration of the previous circuit(More)
Nowadays, one of the challenges for creating a mixed hardware/software application on dynamically reconfigurable SoC is how to provide a unified programming model for hybrid hardware/software tasks and a portable interface adaptation for dynamically reconfigurable hardware tasks. In this paper, a POSIX-compliant hardware thread interface is proposed for(More)
Multimedia processor designers are always challenged by performance, cost and flexibility. Due to the technological advance in FPGA, one of the promising solutions is to enable dynamically reconfigurable SoC in multimedia application. This paper utilizes reconfigurable SoC (RSoC) in multimedia processing. We propose a feasible run-time reconfigurable system(More)
Reconfigurable system provides both flexibility of software and performance of hardware. It is a significant trend in embedded application domain. Some new reconfigurable technologies and technology-dependent tools have been developed, but the whole design flow for run-time reconfigurable systems with real-time operating system support is not proposed. RTOS(More)
The advantages and the flexibility introduced into the hardware implementation by partial dynamic reconfiguration have rapidly changed the design flow of embedded systems. Configuration management is an important issue in operating system for dynamically reconfigurable system-on-chip. Reconfiguration overhead affects the performance of reconfigurable(More)