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- Weijia Shang, José A. B. Fortes
- IEEE Trans. Computers
- 1991

- Weijia Shang, José A. B. Fortes
- IEEE Trans. Parallel Distrib. Syst.
- 1992

Most existing methods of mapping algorithms into processor arrays are restricted to the case where n-dimensional algorithms, or algorithms with 71 nested loops, are mapped into ( n 1)-dimensional arrays. However, in practice, it is interesting to map n-dimensional algorithms into ( k 1)-dimensional arrays where I; < 1 1 . For example, many algorithms at bit… (More)

- Edin Hodzic, Weijia Shang
- IEEE Trans. Parallel Distrib. Syst.
- 1996

With the objective of minimizing the total execution time of a parallel program on a distributed memory parallel computer, this paper discusses how to nd an optimal supernode size and optimal supernode relative side lengths of a supernode transformation (also known as tiling). We identify three parameters of supernode transformation: supernode size,… (More)

- Edin Hodzic, Weijia Shang
- IEEE Trans. Parallel Distrib. Syst.
- 1999

With the objective of minimizing the total execution time of a parallel program on a distributed memory parallel computer, this paper discusses the selection of an optimal supernode shape of a supernode transformation (also known as tiling). We assume that the communication cost is dominated by the startup penalty and therefore, can be approximated by a… (More)

- Weijia Shang, José A. B. Fortes
- IEEE Trans. Computers
- 1992

- Weijia Shang, Matthew T. O'Keefe, José A. B. Fortes
- ICPP
- 1991

- Zhigang Chen, Weijia Shang
- SPDP
- 1992

This paper deals with the problem of transforming irregular data dependence structures of algorithm7 with nested loops into more regular ones. Algorithms under consideration are n-dimensional algorithms (algorithms with n nested loops) with afine dependences where dependences are linear functions of index variables of the loop. Methods are proposed to… (More)

- Weijia Shang, José A. B. Fortes
- ICPP
- 1990

- Weijia Shang, Matthew T. O'Keefe, José A. B. Fortes
- Algorithms and Parallel VLSI Architectures
- 1991

- Weijia Shang, Zhongliang Shu
- ASAP
- 1994