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Exploiting thread level parallelism is paramount in the multicore era. Transactions enable programmers to expose such parallelism by greatly simplifying the multi-threaded programming model. Virtualized transactions (unbounded in space and time) are desirable, as they can increase the scope of transactions' use, and thereby further simplify a programmer's(More)
Many applications written in garbage collected languages have large dynamic working sets and poor data locality. We present a new system for continuously improving program data locality at run time with low overhead. Our system proactively reorganizes the heap by leveraging the garbage collector and uses profile information collected through a low-overhead(More)
As high GHZ processors become prevalent, adding hardware support to ensure the cor-rectness and security of programs will be just as important, for the average user, as further increases in processor performance. The goal of our research is to focus on developing compiler and hardware support for efficiently performing software checks that can be left on(More)
We analyze the performance of different bounds checking implementations. Specifically, we examine using the x86 bound instruction to reduce the run-time overhead. We also propose a compiler optimization that prunes the bounds checks that are not necessary to guarantee security. The optimization is based on the observation that buffer overflow attacks are(More)
PVM Light Weight Process package or PLWP is a multi-threaded environment built over the Parallel Virtual Machine (PVM). Its original purpose was to furnish a laboratory for James Hoe to experiment with thread scheduling strategies in his FUNi project. PLWP has since become more flexible, and now permits user-definable thread scheduling and object-passing(More)
Computer architecture including core microarchitecture design, transactional memory and memory hierarchy. Program analysis for designing specialized co-processors. Algorithmic optimizations for addressing system bottlenecks. Arsenal Processors: Massively Heterogeneous Multiprocessors. The goal of the Arsenal processor design is to use massive heterogeneity(More)