Wei-Yeh Shih

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This paper presents an efficient VLSI implementation of on-line recursive ICA (ORICA) processor for real-time multi-channel EEG signal separation. The proposed design contains a system control unit, a whitening unit, a singular value decomposition unit, a floating matrix multiply unit and, and an ORICA weight training unit. Because the input sample rate of(More)
This paper presents a real-time processing flow for ICA based EEG acquisition system with eye blink artifact elimination. Since EEG signals are one of the feeblest physiological electrical signals, it is easily contaminated by artifacts. Previously, ICA was used to extract artifacts from an EEG data segment in a time period. After processing of ICA,(More)
This paper presents a pipeline VLSI design of fast singular value decomposition (SVD) processor for real-time electroencephalography (EEG) system based on on-line recursive independent component analysis (ORICA). Since SVD is used frequently in computations of the real-time EEG system, a low-latency and high-accuracy SVD processor is essential. During the(More)
This paper presents an online recursive ICA (ORICA) based real-time multi-channel EEG system on chip design with automatic eye blink artifact rejection. Since EEG signals are very feeble, they are easy to be contaminated by artifacts. Among all artifacts, eye blink artifact dose the most significant harm to EEG signals. For acquiring artifact free EEG(More)
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