Wei-Ting Tu

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The electrostatic discharge (ESD) problem has become a challenging reliability issue in nanometer circuit design. High voltages resulted from ESD might cause high current densities in a small device and burn it out, so on-chip protection circuits for IC pads are required. To reduce the design cost, the protection circuit should be added only for the IC pads(More)
Many circuit designs need to follow some temporal rules. However, it is hard to express and verify them in the past. Therefore, a temporal assertion extension to Verilog, called Temporal Wizard, is proposed in this paper. It provides several Verilog system tasks for the users to write assertions in testbench directly. Two new concepts, tag and thread, are(More)
Low dose of D-cycloserine (DCS), a partial agonist of glycine binding site on N-methyl-D-aspartate (NMDA) receptors, can facilitate extracellular signal-regulated kinase1/2 (ERK1/2) activity in the amygdala and modulate emotional behavior. However, the relationship between ERK1/2 activation, individual anxiety levels, and DCS is unknown. Therefore, based on(More)
As the complexity of circuit design increases, verification through simulation has become a bottleneck of the IC design process. Distributed parallel simulation is one way to solving the problem. In order to distribute the simulation workload to multiple processors, the design must be carefully partitioned first. While most previous work focus on gate level(More)
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